Andrzej Wojciechowski
supervisor: Witold Pleskacz
Multiple individual systems clock signal phase alignment is a major issue. Its importance increases with the demand for higher precision, reliability, and speed. Over the years, multiple synchronization methods were invented, but most of them operate in larger time scale (from seconds to individual clock cycles) or are very complicated and aimed for big systems synchronization (such as White Rabbit protocol). This creates a need for simpler phase alignment system that will enable high precision synchronization on sub-clock cycle level. In order to ensure sufficient performance, this kind of system needs to be implemented in an integrated circuit or using specialized hardware.
Clock signal phase synchronization implemented in integrated circuits can enable numerous advantages in digital integrated circuits. The areas which can benefit are multiple devices synchronization or cooperation of individual integrated circuits and more. Furthermore, it may have additional impact on the design and time of development of final products.
Current works include synchronization system’s architecture concept, mathematical model, the calibration algorithm, computer simulations, as well as first prototypes. Next steps include implementation using FPGA chip resources and verification of the idea using FPGA-based prototypes.