Marek KoĊcielski
supervisor: Mariusz Sochacki
The now a days trend in electronics is miniaturization. The shift can be seen in the amount of transistor per area or the amount of space used for components. The packages become multi-functional as System in a Package (SiP) is gaining more attention. Also the build up of components in the Z-axis can be seen in packages such as Package on Package (PoP) or the amount of stacked dies especially in the memory chips. All these trends are especially manifested in the mobile devices where minimizing the of the Printed Circuit Board Assembly (PCBA) enables to fit batteries with higher capacity.
All those trends may lead not only to use the Z axis and populate components on top but also embedding them into the Printed Circuit Board (PCB). Such embedding models with a stack-up will be presented. The focus will be the embedding of the passive components such as capacitors and resistors. Exemplary stack-up and lay-out of the PCB are presented below on figure 1.
Fig. 1 Stack-up of the tested PCB (left), the projection of proposed test coupon internal-layer after assembly (right).
The first assumptions of the project with their expected impact would be presented together with the technical line-out of the embedding process.