Andrzej Wojciechowski
supervisor: Witold Pleskacz
Multiple individual systems synchronization is a major issue. It’s importance increases with the demand for higher precision, reliability and speed. Over the years, multiple synchronization methods were invented, but most of them operate in larger scale (from seconds to individual clock cycles). For higher precision, phase of the clock signal needs to be adjusted. This creates a need for phase synchronization system that will enable high precision synchronization on sub-clock cycle level. This kind of system needs to be implemented in integrated circuit to ensure sufficient performance.
Clock signal phase synchronization implemented in integrated circuits can enable numerous advantages in digital integrated circuits. The areas which can benefit are communication between chips or cooperation of individual integrated circuits and more. Furthermore, it may have additional impact on the design and time of development of final products.
Current works include synchronization system’s architecture concept, coarse mathematical model and early version of the operation algorithm. Computer simulations are in progress. Next steps include the actual design of the system and actual parameters extraction for further simulation.