Marika Grochowska
supervisor: Witold Pleskacz
Today, there are many tools for verifying technological masks of integrated circuits. However, there are still areas, especially in large analog circuits, where the designer is unable to catch all the issue. One of this which we struggle in the company that I work is verifying connections between metals, so-called VIAs. It often happens that due to porting projects, VIA contacts are meaningfully reduced which is difficult to catch especially in large design with high numbers of metals. This is why one of the goals of my PhD is to create program which finds places where additional VIA contact can be added between the conductive paths. The algorithm is written in the Physical Verifcation Language that is compatible with Cadence tools such as PVS or Pegasus. First, the algorithm analyzes the topography of the chip and take into account the physical connections between the metals that make the conductive paths. Then, according to the design rules for a given technology, it searches for places where additional contacts (VIA) can be placed without breaking the design rules and not causing short between different conductive paths. Thanks to the placement of additional VIA contacts, the path resistance is reduced, which significantly improves the efficiency of the system. Program with some additional functions was written and successfully implemented in company. Right now, is one of the basic checks that is run on designed topography before delivery.