Andrzej Wojciechowski
supervisor: Witold Pleskacz
Phase difference of the clock signals is a critical factor in high precision synchronization of interconnected integrated circuits. In order to synchronize a daisy-chained set of individual systems, a novel concept of clock signal phase alignment circuit as well as calibration algorithm was developed. The work includes a high-level analog circuit description and calibration procedure implemented in digital control module. The high-level implementation was tested using Verilog HDL language and conclusions are presented.
The motivation of this work is to develop a clock signal phase alignment for a system composed of individual ASIC devices. One of the use cases for the ASIC and the described system is a vacuum chamber actively cooled down to cryogenic temperature. Due to other requirements, multiple units of the designed ASIC system will be connected using as few signals as possible, hence a daisy chain connection topology.
The proposed circuit for clock signal phase alignment together with the calibration algorithm is presented. The calibration algorithm was confirmed to work correctly. The general idea was implemented with Verilog HDL language and functionally verified. The presented concept is an on-going work and will be researched and developer further using a FPGA-based prototype as well as a dedicated ASIC system.